Description
NXP is hiring a Lead PERC Rule Developer in India to own PERC methodology, rule-deck development, debugging, validation, automation, and flow enablement for ESD, latch-up, power-domain, connectivity, and reliability verification. The role supports physical verification across IP, block, subsystem, and SoC design stages, collaborates with design, CAD, technology, foundry/interface, and product teams, and mentors junior engineers. It requires a relevant engineering or microelectronics degree, at least 10 years of industry experience, strong Calibre PERC/LVS expertise, scripting, analog/mixed-signal and CMOS/FinFET knowledge, and leadership and communication skills.
