Description
Micron is hiring a Lead Principal Engineer, Layout Design to lead the physical implementation of new DRAM and mixed-signal memory products. The role covers hierarchical layout, floorplanning, physical verification, parasitic extraction, tapeout signoff, ECO coordination, and cross-team integration, while also driving layout methodology and resource planning. Candidates need at least 10 years of semiconductor experience, a relevant bachelor's degree or equivalent experience, CMOS and layout knowledge, custom IC layout and physical verification experience, and scripting or automation proficiency.
