Description
The role develops and maintains RTL for digital blocks, writes and runs simulations, debugs functional issues, supports integration, and collaborates with verification and physical design teams. Responsibilities also include synthesis, linting, timing checks, and documenting design behavior, assumptions, and interfaces. Required skills include RTL design with Verilog or System Verilog, digital electronics fundamentals, simulation and debugging, ASIC design flow, EDA tools, version control, and strong communication and documentation skills.
