Description
Cadence is seeking a Functional Verification Engineer to design, develop, verify, and deploy Verification IP. The role requires 3 to 5 years of domain experience, proficiency in functional verification and test environment creation using SystemVerilog/UVM, knowledge of C/C++ and scripting, and experience with layered protocols such as UCIe, PCIe, CXL, and Ethernet. The engineer will collaborate cross-functionally with customers and demonstrate strong analytical, communication, adaptability, and problem-solving skills.
