Description
Cadence is hiring a synthesizer development engineer to develop and maintain the Palladium synthesizer, implement new VHDL/Verilog feature support, and improve logic optimization and performance. The role requires a bachelor's or master's degree in EE, CS, or CE, 3–5 years of industry experience, C/C++ and operating-system knowledge, RTL modeling, and familiarity with EDA/CAD tool development or logic design verification; UVM, SC/TLM, AI coding tools, and communication skills are also mentioned.
