Description
The Standard Cell Library Engineer will develop and characterize standard cell libraries, including differentiated IP augmentation and internalization of third-party IP. The role covers standard cell and macro characterization, layout design, EDA development, circuit and MC simulation, layout-dependent effects, RTL-to-GDS flow, STA and PnR, and the characterization of NLDM, CCSP, CCSN, AOCV, and LVF models. The position requires 7–9 years of experience in the standard cell domain, knowledge of CMOS and FinFET technologies, and expertise with EDA tools from Siemens, Cadence, and Synopsys.
