Logic Design/Verification Sr Staff Engineer at Synopsys

Location: Dublin
Level: lead/mgmt
Posted: Sep 7, 2026

Description

Synopsys is seeking a senior verification leader to architect and implement UVM-based verification environments for interface IP, develop System Verilog test sequences and assertions, drive functional and code coverage, and lead and mentor a team of verification engineers. The role requires a bachelor’s or master’s degree in a relevant engineering field, at least eight years of ASIC design verification experience, and strong expertise in System Verilog, constrained random verification, and verification methodologies.

Required Skills

UVM verification
System Verilog
Constrained random
System Verilog Assertions
Coverage analysis
Formal verification
PCI Express
CXL protocols

Additional Information

Minimum Education: Bachelor’s or master’s degree in computer engineering, Electrical Engineering, or Communication Engineering
Required Previous Experiences: 8+ years of hands-on ASIC design verification experience focused on UVM-based functional verification
Experience implementing System Verilog Assertions for functional and formal verification flows
Experience with PCI Express and CXL protocols
Preferred Qualifications: Programming skills in at least two of C, System Verilog, TCL, Perl, or Python
Experience with interface IP verification, formal verification tools, and AI-assisted coding tools