The LPDDR PHY IP team is hiring a Digital ASIC Verification Engineer to develop test benches and verify integrated IP subsystems for global customers. The role requires a BSEE with at least six years of relevant experience or an MSEE with at least three years of relevant experience, along with ASIC RTL design and verification experience, strong Verilog, SystemVerilog, UVM, Perl, and TCL skills, silicon debugging knowledge, and Mandarin and English communication skills.
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