Machine Learning Hardware Architect at IMC Trading

Compensation

$200,000 – $225,000/yr

Location: Town of Cortlandville, New York
Type: Full-time
Posted: Feb 27, 2026

Description

This role involves designing, implementing, and deploying machine learning engines on custom hardware, specifically focusing on FPGA or ASIC technologies. The successful candidate will collaborate with traders, quantitative researchers, and software engineers to optimize ML models for efficiency and achieve low latency. They will also contribute to researching and building advanced techniques like neural network quantization and compression, translating high-level ML frameworks into RTL designs. The company emphasizes rapid iteration due to its collaborative culture and unified codebase, allowing immediate deployment of innovations.

Required Skills

FPGA
ASIC
VHDL
Verilog
SystemVerilog
Digital Design Principles
Pipelining
Flow Control
Clock Domain Crossing
Python
C++

Additional Information

Required Previous Experiences: Extensive experience with FPGA or ASIC technologies, including proficiency in either VHDL, Verilog, or SystemVerilog
Solid understanding of digital design principles, including pipelining, flow control, and clock domain crossing
Experience with FPGA development tools and toolchains (Vivado, Quartus, Synplify, etc.)
Understanding of machine learning fundamentals – neural network architectures, inference optimization, quantization techniques
Experience optimizing inference for temporal or sequential ML models (RNNs, Transformers, state-space models) on resource-constrained or latency-sensitive platforms
Proficiency in Python, C++, or similar languages for tooling, testing, and simulation
Preferred Qualifications: Experience with High-Level Synthesis (HLS) or other hardware description languages beyond traditional RTL
Familiarity with ML-to-hardware frameworks such as hls4ml, FINN, or Vitis AI
Experience with ML-relevant compiler intermediate representations and optimization passes such as MLIR, LLVM, polyhedral analysis, or production ML compilers (TVM, XLA, IREE)
Background in ultra-low-latency systems – whether in high-frequency trading, particle accelerator data acquisition, real-time signal processing, or similar applications
Experience with functional verification methodologies (SystemVerilog, UVM, Cocotb)