Manager Design Verification at Astera Labs

Astera Labs is hiring a Manager Design Engineer to architect and deliver connectivity silicon for AI infrastructure. The role owns RTL design and implementation of complex blocks, develops synthesizable Verilog/SystemVerilog, and leads design reviews, timing closure, CDC, lint, and tapeout activities. The engineer partners with architecture, verification, DFT, and physical design teams, mentors junior engineers, and debugs pre- and post-silicon issues. The position requires a bachelor's degree in electrical or computer engineering, at least five years of digital design experience including a full chip from specification to tapeout, and strong proficiency in RTL, synthesis, timing closure, CDC, and high-speed serial interfaces.