Memory Design Engineering Manager at Synopsys

Language

Location: Da Nang
Type: Full-time
Level: lead/mgmt

Description

Synopsys is hiring a Memory Design Engineering Manager in its Silicon IP business unit in Da Nang to lead embedded memory IP development across advanced process nodes. The role involves managing architecture, circuit design, physical implementation, modeling, simulation, design reviews, documentation, and silicon evaluation for SRAM, register files, TCAM, and ROM, with a strong emphasis on 5nm/7nm-class design, variation-aware engineering, and team mentorship.

Required Skills

Circuit design
VerilogA
SystemVerilog
ASIC design flow
Memory IP
Team management

Additional Information

Minimum Education: Bachelor's or Master's degree in Electrical Engineering, Computer Science, or equivalent
Required Previous Experiences: 10+ years of embedded memory design experience
Experience managing engineering teams
Preferred Qualifications: Expertise in SRAM, register file, TCAM, and ROM architectures
Experience with advanced-node (7nm, 5nm or beyond) memory design and variation-aware design
Knowledge of digital design, verification methodologies, ASIC design flow, and EDA tools
Ability to review schematics and catch timing issues
Proficiency in VerilogA modeling
Mentoring and coaching engineers

About Synopsys

Synopsys

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