Description
Synopsys is hiring a Staff Memory Layout Design Engineer to design and own custom layouts for SRAM, register files, ROM, and related memory compiler IP blocks from floorplan through final signoff. The role executes DRC, LVS, ERC, antenna, density, and reliability checks; drives technology-node migrations; collaborates with circuit designers; develops Tcl, Perl, or Python automation and layout methodologies; reviews junior engineers’ work; and supports customer-specific memory customization projects. The position requires a bachelor’s or master’s degree in electronics, VLSI, microelectronics, or a related technical field.
