Memory Layout Designer at Client Diagnostics

Location: Ottawa, Ontario

Description

This job posting seeks an experienced individual with 5 to 10 years of experience in memory layout design, specifically focusing on building top-level instances using Memory Compilers. The candidate should possess advanced knowledge of design rule, yield, and reliability considerations, particularly EM-IR, HCI, and NBTI. They must also have direct hands-on experience in transistor, cell, and block-level memory layout design for various FinFET process technologies such as 3nm/5nm/7nm/10nm/14nm. A strong understanding of CMOS semiconductor processes is essential.

Required Skills

Memory Layout Design
Design Rules
Yield
Reliability
EM-IR
HCI
NBTI

Additional Information

Required Previous Experiences: 5 to 10 years in memory layout design
building top level instances with Memory Compilers
Preferred Qualifications: Advanced knowledge of design rules, yield and reliability issues (EM-IR, HCI and NBTI).
Must have transistor, cell and block level memory layout design hands on experience in either of 3nm/5nm/7nm/10nm/14nm FinFET process technology for memory layout
Knowledge of CMOS semiconductor...