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Memory Package Integration Architect at Micron

Department: Assembly & Test

Compensation

$143,000 – $398,000/yr

Setup
On-site
Location
Boise, Idaho · San Jose, California
Type
Full-time
Level
senior
Posted

Description

Micron Technology is hiring a Technical Pathfinding Engineer to define next-generation packaging and system architectures for memory systems spanning datacenter to edge-AI. The role leads cross-stack co-optimization across silicon, package, board, and system; drives long-term packaging strategy and industry standards; partners with customers and internal teams; and develops AI-based multi-physics solutions. Candidates need a master’s degree or equivalent practical experience in a relevant technical field, at least six years of hands-on memory systems packaging experience, and expertise in memory timing, signaling, power, packaging process technology, EDA tools, and AI or LLM engineering efficiency.

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