Description
Samsung is hiring a Micro-Architect/Logic Designer to lead the development of custom coherent interconnect IP and last-level cache blocks for high-performance computing devices. The role owns RTL design, microarchitecture specification, verification, performance and power optimization, timing closure, logic debug, and implementation collaboration, while also mentoring junior engineers. Candidates need substantial experience in high-performance digital design, Verilog, ASIC design flows, and coherent interconnect or cache protocols, with education and experience requirements varying by degree. The role offers a base-pay range of $151,000 to $251,800 and includes medical, dental, vision, retirement, and other benefits.
