Microarchitect / RTL Design - Interconnect & Fabric at Architect

Department: Hardware

Setup: On-site
Location: Palo Alto, California
Level: senior
Posted: Aug 12, 2026

Description

Architect is hiring an RTL Design Engineer to own the AI-driven microarchitecture and RTL design of on-chip interconnect fabrics and high-speed I/O data movement subsystems for production silicon. The role covers NoC routers, crossbar switches, AXI/ACE/CHI and other AMBA-based fabrics, PCIe/CXL and UCIe bridges, peer-to-peer DMA engines, interface specifications, RTL automation, verification support, FPGA prototyping, and PPA closure. Candidates need a degree in electrical or computer engineering, at least five years of RTL design experience including advanced-node tapeout experience with on-chip interconnects, and expertise in AMBA protocols, NoC design, high-speed I/O, SystemVerilog, Python, and SoC methodology.

Required Skills

AMBA protocols
NoC design
High-speed I/O
Peer-to-peer DMA
SystemVerilog
Python
SoC methodology
FPGA prototyping

Additional Information

Minimum Education: Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a closely related field
Required Previous Experiences: 5+ years of RTL design experience, including at least one advanced-node tapeout involving on-chip interconnects, NoC fabrics, or high-speed I/O subsystems
Experience with HSIO bridge logic, including PCIe/CXL bridges, UCIe, or custom chip-to-chip links
Experience with peer-to-peer DMA architectures and zero-copy data transfer engines
Experience taking an interconnect or fabric block from RTL through synthesis and working with PD teams on timing, area, and power closure
Preferred Qualifications: Experience with coherent multi-chip or multi-die interconnect architectures
Familiarity with hardware coherence protocols
Experience with NoC research, adaptive routing, congestion management, topology optimization, or formal deadlock analysis
Low-power interconnect design techniques
FPGA prototyping experience with Xilinx Vivado/Vitis and AXI/NoC IPs
SVA assertions for protocol compliance
Prior IP building and delivery experience for NoC, AXI, PCIe, or CXL IPs
Performance modeling with NoC simulators or system-level traffic models
Domain-specific research contributions in on-chip networks, interconnect architectures, or high-performance data movement