Microarchitect / RTL Design - Memory Subsystem at Architect

Department: Hardware

Setup: On-site
Location: Palo Alto, California
Level: senior
Posted: Aug 12, 2026

Description

Architect is hiring an RTL Design Engineer to own the AI-driven memory subsystem for production custom silicon. The role covers memory controllers, memory hierarchy, memory-side accelerators, interface specifications, RTL infrastructure, verification support, FPGA prototyping, and collaboration with architecture, software, machine learning, and physical design teams. Candidates need a degree in electrical or computer engineering, at least five years of RTL design experience including advanced-node tapeout experience with memory subsystems, and expertise in DDR, HBM, cache, SoC methodology, Python, and PPA closure.

Required Skills

DDR5/LPDDR5X
HBM3/HBM3E
Cache controllers
SystemVerilog
Python
Timing closure
FPGA prototyping

Additional Information

Minimum Education: Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a closely related field
Required Previous Experiences: 5+ years of RTL design experience, including at least one advanced-node tapeout involving memory subsystems
Experience designing or owning memory controller blocks
Experience with multi-level cache design or unified memory architectures
Experience taking a memory controller or cache subsystem from RTL through synthesis and PPA closure
Preferred Qualifications: HBM integration experience
CXL or disaggregated memory architecture experience
Near-memory or processing-in-memory design experience
Low-power memory design techniques
Xilinx FPGA prototyping experience
SVA assertions for JEDEC compliance
Prior IP building and delivery experience
Memory system performance modeling
Research contributions in memory systems or ML-centric architectures