Description
Micron Technology is hiring a Senior Layout Engineer for its DRAM Engineering Group in India. The role leads full-chip and block-level analog and memory layout design, establishes layout standards and verification practices, manages multiple projects and tape-outs, guides junior engineers, and collaborates with global design, verification, CAD, and cross-functional teams. The position requires 15+ years of analog/custom layout experience in advanced CMOS, expertise in Cadence VLE/VXL and Calibre DRC/LVS, hands-on experience with analog blocks and memory technologies, scripting and automation experience, and a BE or MTech in Electronic/VLSI Engineering.
