Description
Qualcomm India Private Limited is seeking a Synthesis Engineer/Lead for its NPU design team. The role owns RTL-to-gate synthesis and timing closure for high-performance AI/ML accelerator IPs and subsystems, develops synthesis flows and constraints, performs pre- and post-layout timing signoff, optimizes designs for performance, power, and area, and collaborates with architecture, RTL, STA, DFT, and physical design teams through tapeout. The position requires a bachelor's, master's, or PhD in a relevant engineering field, at least 2–4 years of hardware engineering experience depending on the degree, and expertise in ASIC design flows, synthesis tools, PrimeTime, UPF, TCL, and scripting.
