Description
Qualcomm India Private Limited is seeking a Synthesis Engineer/Lead for its NPU design team to own RTL-to-GDS synthesis and timing closure for high-performance AI/ML accelerators. The role develops synthesis flows and constraints, performs pre- and post-layout timing closure, optimizes designs for performance, power, and area, collaborates with architecture, RTL, STA, DFT, and physical design teams, and supports tapeout and continuous synthesis improvements. The position requires a relevant bachelor's, master's, or PhD degree, at least one year of hardware engineering experience depending on the degree, and expertise in ASIC design flows, synthesis tools, timing analysis, low-power methodologies, and scripting.
