Description
Qualcomm India Private Limited is hiring an NPU Synthesis Lead to drive RTL-to-gate synthesis and timing closure for Neural Processing Unit IP and subsystems in advanced SoCs. The role owns synthesis flows, timing closure, PPA optimization, constraint management, quality checks, and flow innovation, while collaborating with architecture, RTL, DFT, and physical design teams and mentoring junior engineers. Candidates need a bachelor’s, master’s, or PhD in a relevant field and substantial ASIC synthesis and timing closure experience, including NPU or AI processor design.
