Description
The Package Design Engineer will lead the physical design and integration of advanced semiconductor packages across SoC, memory, RF, and cellular technologies. The role owns package, SiP, and module architecture from concept through tape-out, optimizes structure and configuration, collaborates with cross-functional teams on SI/PI performance, and uses AI tools to improve design efficiency, quality, and performance. The position requires a bachelor's degree and at least 10 years of relevant industry experience, with preferred expertise in Cadence Allegro or Mentor Xpedition, high-speed interfaces, SI/PI analysis, manufacturing processes, and automation scripting.
