Description
Intel is hiring a Packaging and Assembly Engineer to support root-cause determination of assembled-package yield loss and in-line failures on a back-of-week compressed shift. The role involves hands-on laboratory work, electrical fault isolation, defect and process characterization, failure-analysis techniques, data acquisition and analysis, and consultation with internal and customer teams. It is lab-based and on-site in Phoenix, Arizona, with a Shift 5 schedule covering the front half of the week from Sunday through Tuesday and alternating Wednesday days. A bachelor's degree in a relevant engineering or science field, US citizenship, and the ability to obtain a US Government TS/SCI security clearance with polygraph are required; hands-on experience with electrical fault isolation or defect characterization is also required.
