Description
Annapurna Labs is hiring a Package Layout Design Engineer to execute physical design of advanced IC packages for machine-learning and data-center ASICs. The role covers floor planning, bump and pad assignment, RDL and substrate routing, verification, tape-out release, and design closure across architectures such as 2.5D interposers, 3D-IC, fan-out WLP, and silicon bridges. The engineer will collaborate with SI/PI, thermal, manufacturing, OSAT, and foundry teams and support DFM compliance. A bachelor's degree in electrical engineering or a related field and at least five years of IC package layout and physical design experience are required.
