PCB Layout Engineer at Kandou AI

Department: Engineering

Language

Setup: On-site
Location: Taipei
Level: senior
Posted: Aug 26, 2026

Description

Kandou is hiring a PCB Layout Engineer in Taipei, Taiwan to design high-speed, multi-layer PCBs for AI hardware products. The role owns the layout from initial floorplan through fabrication and assembly data release, translating schematics into DFM-compliant designs while managing controlled impedance, differential routing, power delivery, EMC/EMI, SI/PI, and fabrication specifications. Candidates need at least five years of professional PCB layout experience, familiarity with high-speed interfaces and EDA tools, and a bachelor's degree in a relevant technical field.

Required Skills

High-speed PCB layout
Controlled impedance
Differential routing
Power delivery design
EMC/EMI design
Cadence Allegro
DFM
DFA

Additional Information

Minimum Education: Bachelor's degree in Electrical Engineering, Electronics Engineering, or a related technical field
Required Previous Experiences: 5+ years of professional PCB layout experience
Hands-on experience designing complex, multi-layer PCBs for high-speed digital interfaces
Proficiency with Cadence Allegro, Mentor/Siemens Xpedition, or PADS
Experience applying IPC standards and DFM/DFA guidelines
Experience working with PCB fabrication and assembly partners
Experience implementing SI/PI guidelines in physical layouts
Experience with schematic capture tools and BOM management
Preferred Qualifications: Experience in semiconductor, server hardware, or high-speed electronics
Familiarity with Taiwan and/or Asian PCB fabrication and OSAT ecosystems
Mandarin proficiency for coordination with local partners and teams
Professional training or certification in PCB design tools and methodologies