PCIe Design Engineer at Google

Seniority in posting: Advanced

Compensation

$192,000 – $278,000/yr

Location: Sunnyvale, California
Type: Full-time
Level: senior
Posted: Sep 16, 2026

Description

Google is hiring a PCIe Design Engineer to architect and implement SoC-level RTL for next-generation data-center accelerators, including PCIe subsystems, clocking, reset, error handling, and chip management. The role leads PCIe microarchitecture and RTL development, coordinates integration with system architects, verification, and physical design, and leads post-silicon bring-up. Candidates need a bachelor's degree in a relevant engineering or computer science field and 10 years of ASIC design experience, including PCIe logic; the position offers $192,000–$278,000 USD plus a 20% bonus target, equity, and benefits.

Required Skills

PCIe microarchitecture
RTL development
SystemVerilog
Clock domain crossing
Timing closure
Post-silicon bring-up
Python

Additional Information

Minimum Education: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
Required Previous Experiences: 10 years of ASIC design experience, including one project focused on PCIe logic
Experience debugging RTL using Verdi/VCS and automating tasks via Python or Perl
Experience in SystemVerilog/Verilog for RTL development and microarchitecture definition
Experience with PCIe protocol layers or LTSSM
Experience with Clock Domain Crossing, timing closure, or synthesis flows
Preferred Qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science with an emphasis on computer architecture
10 years of ASIC design experience, including 3 years in PCIe Gen4/5/6 controller or protocol logic
Experience with advanced RTL design, including multi-clock domains, timing closure, datapath optimization, and hardware/firmware partitioning
Experience with cross-functional leadership from RTL development through silicon bring-up
Experience in PCIe architecture, including LTSSM, TLP/FLIT pipelines, flow control, ordering rules, and performance tuning
Knowledge of ASIC flow, SerDes, and scripting