Description
The role performs ASIC/SoC physical design, including floorplanning, placement, clock tree synthesis, routing, static timing analysis, power and IR-drop analysis, physical verification, ECO implementation, and design closure. It requires knowledge of ASIC/SoC design flows, process technologies, signal integrity, scripting, and tools such as Synopsys, Cadence, and Mentor Graphics, along with a bachelor’s or master’s degree in a relevant engineering field and 2–10 years of physical-design experience.
