Description
NVIDIA is hiring a Static Timing Analysis (STA) Physical Design Engineer for its Networking team in Israel. The role performs chiplet and fan-out-level STA, uses Prime Time to review and debug timing paths, generates SDC and timing ecosystem files, identifies convergence risks, and manages timing closure and quality approval from pre-layout through signoff. Candidates need a B.Sc. in Electrical or Computer Engineering, 2–3 years of STA engineering experience, strong adaptability, communication skills, and teamwork ability; knowledge of physical build flows and Prime Time is advantageous.
