Description
NVIDIA is hiring a Physical Design CAD Engineer for its Networking Silicon engineering team to develop physical design, synthesis, static timing analysis, and logic-equation methodologies for networking chips and SOCs. The role involves collaborating with block owners, chip STA engineers, and project managers; solving advanced physical design problems; and contributing to floorplan, power and clock distribution, placement and routing, timing closure, power and noise analysis, and back-end verification. Candidates need an electrical or computer engineering degree or equivalent experience, at least two years of relevant experience, scripting proficiency, deep-sub-micron convergence expertise, physical design optimization knowledge, process-variation experience, and a successful production-delivery record. Familiarity with Synopsys and Cadence EDA tools and experience owning synthesis, place-and-route, or STA flows are advantageous. The position is hybrid.
