Physical Design Engineer at taiwansemiP1

Compensation

$110,000 – $160,000/yr

Location: San Jose, California
Level: not_specified

Description

Join TSMC's Test Chip Physical Implementation team in San Jose, CA, as a highly motivated and skilled Physical Design Engineer. This role involves driving the end-to-end physical implementation and tapeout of test vehicles on TSMC’s leading-edge process nodes (A16/A14/A10). Responsibilities include executing comprehensive physical design flows, performing rigorous design signoff verification, developing CAD automation scripts, and collaborating with cross-functional teams.

Required Skills

VLSI design
EDA tools
Block and SoC-level floorplanning
power grid implementation
low-power structure integration
Advanced placement
clock tree synthesis (CTS)
routing
design optimization
RC extraction
Static Timing Analysis (STA)
IR/EM analysis (IREM)
Design Rule Check (DRC)
Layout Versus Schematic (LVS)
Electrical Rule Check (ERC)
Voltage-Aware Layout Parasitic (VCLP) analysis
CAD automation scripts
TCL
Python
CSH
Verilog
Unix shell scripting

Additional Information

Minimum Education: Master’s Degree or higher in Electrical Engineering or Computer Science
Required Previous Experiences: at least 3 years of industrial experience
Preferred Qualifications: Prior internship or professional experience in physical design, circuit design, or related semiconductor roles.
Experience in optimizing placement strategies, congestion removal, and post-placement timing closure.
Familiarity with clock tree synthesis techniques to mitigate latency and skew.
Knowledge of Power Integrity (PI) and Signal Integrity (SI) closure techniques.
Experience with multi-voltage design concepts and low-power techniques.
Familiarity with other EDA tools such as Ansys Redhawk or Synopsys Fusion Compiler.
DFT knowledge is a plus.