Description
The Physical Design Engineer performs RTL-to-GDS physical design implementation for custom IP and SoC designs, including synthesis, placement and routing, clock-tree synthesis, floor planning, static timing analysis, power and clock distribution, reliability, and signoff. The role analyzes design violations, recommends fixes, and optimizes power, frequency, and area while participating in flow automation and mentoring junior team members. It requires a bachelor's degree in computer or electronic engineering and at least three years of relevant experience, including deep-submicron tape-outs, physical-design flows, EDA tools, scripting, and hardware-description languages.
