Description
The role leads physical design for custom silicon, partnering with RTL, architecture, DFT, and technology teams to optimize power, performance, and area. Responsibilities include block- and IP-level design from synthesis through place and route, timing-path debugging, EDA-tool optimization, and signoff activities such as static timing analysis, timing and power recovery, and electrical and layout checks. The position requires a bachelor's degree in electrical engineering, computer science, or a related field, or equivalent practical experience, plus eight years of high-speed design experience involving implementation and PPA optimization.
