Description
This role involves performing physical design implementation of custom IP and SoC designs from RTL to GDSII, creating a design database for manufacturing. The individual will conduct all aspects of the physical design flow, including synthesis, placement and routing, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power/noise analysis. Verification and sign-off processes like formal equivalence verification, static timing analysis, reliability verification, and layout verification will also be conducted. The person will analyze results, make recommendations for fixing violations, and optimize designs to enhance product-level parameters such as power, frequency, and area. They will participate in developing and improving physical design methodologies and flow automation.
