Description
NXP Semiconductors is hiring a Physical Design Engineer (G2) for its VLSI team to implement and sign off complex SoC and IP blocks in advanced technology nodes. The role covers floorplanning, power grid design, placement, clock tree synthesis, routing, timing convergence, DRC/LVS, IR drop, electromigration, congestion, SI, and physical ECOs, while collaborating with RTL, DFT, packaging, and integration teams. Candidates need a bachelor’s or master’s degree in electronics, electrical, or microelectronics engineering, 3–5 years of ASIC physical design experience, advanced-node experience, EDA tool knowledge, and scripting skills.
