Description
Renesas is hiring a Physical Design Engineer for its Analog Backend team to implement digital-island physical design in mixed-signal analog chips. The role covers floorplanning, placement optimization, clock tree synthesis, routing, physical verification, performance, reliability, and manufacturability optimization, as well as chip-level power-integrity analysis across multiple voltage domains. The engineer will collaborate with analog designers and verification engineers and should have ASIC physical design experience, including floorplanning, placement, CTS, routing, and sign-off checks, along with knowledge of IR drop and electromigration analysis.
