Description
The Physical Design Engineer will own block and full-chip physical implementation of complex logic for the Tensor SOC GPU, managing power, performance, area, timing, electromigration, and signoff convergence. The role collaborates with RTL, DFT, and Foundation IP teams and uses AI physical design workflows to improve productivity, time to market, and PPA. A bachelor's degree in a relevant engineering or computer science field and four years of physical design experience with at least two chip tape outs are required.
