Description
The employer is hiring Static Timing Analysis engineers to support a leading SoC manufacturer on advanced-node designs. The role owns timing constraints, block- and full-chip timing signoff, timing closure, signal integrity, parasitic correlation, variation-aware analysis, hierarchical timing, low-power timing, and flow automation. Candidates need strong static timing fundamentals, hands-on experience with Synopsys PrimeTime or PrimeTime SI, SDC proficiency, MMMC analysis, advanced-node exposure, and strong TCL scripting skills; Python or Perl is also useful. The posting welcomes candidates with 3–8 years of experience and requires a degree in electronics, electrical engineering, VLSI design, microelectronics, or a related discipline.
