Description
NVIDIA is hiring a Physical Design Engineer to join its Networking Silicon engineering team and develop high-speed communication chips. The role owns RTL-to-gate synthesis and quality-of-result convergence, optimizes synthesis strategies and constraints, analyzes design bottlenecks, supports physical implementation through floorplanning, power planning, routing, and timing closure, and automates design workflows. Candidates need a BSEE, MSEE, or equivalent experience, at least two years of synthesis and physical implementation experience on advanced process nodes, proficiency with Synopsys Fusion Compiler, Cadence Genus, or comparable tools, and knowledge of Python, Perl, Tcl, and Make. The base salary range is 116,000 USD to 189,750 USD for Level 2 and 136,000 USD to 218,500 USD for Level 3, with equity and benefits available.
