Description
Qualcomm is hiring an ASIC Physical Design Engineer to own end-to-end physical design and PPA optimization across synthesis, floorplanning, placement, clock-tree synthesis, routing, timing closure, and physical signoff. The role requires advanced-node experience, low-power implementation, multi-clock-domain and multi-corner/multi-mode timing closure, and proficiency with industry-standard synthesis and PnR tools. Candidates need a bachelor's, master's, or PhD in a science, engineering, or related field plus the stated years of ASIC design or related experience, with Python/Tcl, scripting, and design-verification experience preferred. The listed pay range is $145,600 to $218,400.
