Description
The role is responsible for the physical design of complex SoCs, including clocking structures, floorplanning, pin placement, power busing, block and macro placement, place-and-route, signal integrity, power and clock analysis, timing closure, noise analysis, and DRC/LVS. It is intended for a new graduate student with an electrical, electronics, telecommunications, or computer engineering technology major, a thesis or related project involving VLSI, VHDL, System Verilog, synthesis, design for test, or physical design, and strong English and presentation skills.
