PMTS ASIC Digital Design IP ENGINEERING at GlobalFoundries

Department: Engineering

Compensation

$167,000 – $275,000/yr

Setup: On-site
Location: California
Type: Full-time
Level: lead/mgmt
Posted: Aug 10, 2026

Description

GlobalFoundries is hiring a PMTS Digital Design Engineer to lead the architecture implementation, microarchitecture development, and RTL design of high-performance processor cores and subsystem components. The role involves translating architectural specifications into Verilog/SystemVerilog, optimizing performance, power, area, and scalability, leading design initiatives, mentoring engineers, and collaborating with verification, physical design, DFT, firmware, and software teams through silicon bring-up and production ramp. Candidates need a bachelor's or master's degree in electrical or computer engineering or a related field and at least 12 years of processor, CPU, DSP, or complex SoC digital design experience. The expected salary range is $167,000 to $275,000.

Required Skills

Processor microarchitecture
RTL design
Verilog/SystemVerilog
Pipeline design
Cache architectures
Branch prediction
Memory hierarchy
MMU/TLB design
Synthesis and timing analysis
Debugging and problem-solving

Additional Information

Minimum Education: Bachelor's or master's degree in electrical engineering, Computer Engineering, or a related field
Required Previous Experiences: 12+ years of processor, CPU, DSP, or complex SoC digital design experience
Preferred Qualifications: Experience with RISC-V, ARM, MIPS, ARC, or custom CPU architectures
Knowledge of multi-core and heterogeneous computing systems
Experience in AI/ML acceleration, vector processing, or advanced computing architectures
Experience with performance modeling and architectural simulation
Silicon bring-up and post-silicon debug experience
Exposure to safety-critical designs under ISO 26262 or DO-254
Translation Company Name: GlobalFoundries