Description
Astera Labs is hiring a Post-Silicon Validation Engineer to perform hands-on post-silicon validation of PCIe connectivity, debug link-training, LTSSM, equalization, recovery, resets, and link-stability issues, and drive complex hardware, firmware, and software problems to resolution. The role also involves developing validation plans, stress tests, corner-case and interoperability tests, and automation for regression testing. Candidates need a BS/MS in a relevant engineering or computer science field, at least five years of silicon validation, post-silicon debug, or high-speed interface experience, strong PCIe knowledge, and experience with analyzers, traces, registers, logs, eye diagrams, and signal-integrity measurements.
