Description
Astera Labs is hiring a Principal Advanced Packaging Engineer to lead R&D for next-generation optical-chip packaging technologies, including NPO and CPO products. The role covers 2.1D, 2.5D, and 3D integration; wafer-, panel-, and die-level packaging flows; EIC-to-PIC integration; materials qualification; OSAT and tool-vendor partnerships; yield, reliability, and process capability; and PDK and design-rule development. Candidates need a relevant advanced degree, at least 8 years of semiconductor or advanced packaging engineering experience, and demonstrated technical leadership.
