Description
Astera Labs is hiring a Principal Analog Design Engineer to architect and design high-performance analog and mixed-signal circuits for SerDes, PHY, and high-speed I/O in advanced FinFET processes. The role owns designs from specification through silicon bring-up, leads characterization and debug, defines analog design standards, partners with cross-functional teams, and mentors junior engineers. Candidates need an MS or PhD in electrical engineering or a related field, at least 8 years of analog and mixed-signal IC design experience, and expertise in high-speed circuits, signal integrity, and design tools such as Cadence Virtuoso and Spectre. The salary range is $207,000 to $230,000, with possible discretionary bonus, incentives, and benefits.
