Description
Astera Labs is hiring an Analog/Mixed-Signal Circuit Design Engineer to design high-speed analog and mixed-signal circuits for multi-gigabit wireline transceiver intellectual property targeting FinFET technology nodes. The role covers PLL, CDR, TX driver, RX front-end, CTLE, DFE, LDO, bias generator, and ADC/DAC design; transistor-level simulation and optimization; layout collaboration; pre- and post-layout verification; silicon bring-up, measurement correlation, and debugging. Candidates need a bachelor’s or master’s degree in electrical engineering, microelectronics, or a related field, plus at least 8 years of analog/mixed-signal circuit design experience in deep-submicron or FinFET technologies.
