Principal ASIC Design Engine at NXP

Location: Hyderabad, Telangana
Type: Full-time
Level: senior
Posted: Jul 16, 2026

Description

NXP is hiring a Principal ASIC Design Engineer specializing in digital RTL design for AI inference SoCs in Hyderabad. The role owns hardware features from microarchitecture and specification through RTL, integration, synthesis, debug, and silicon bring-up, while collaborating with architecture, verification, DFT, physical design, firmware, and systems teams. Candidates need 14+ years of ASIC/SoC RTL design experience, strong Verilog/SystemVerilog skills, and expertise in synthesis, timing, power, lint, CDC, RDC, and debugging.

Required Skills

Verilog/SystemVerilog
AI SoCs
Microarchitecture
RTL design
Synthesis
Timing analysis
Power analysis
Lint/CDC/RDC
Debugging
Timing closure

Additional Information

Required Previous Experiences: 14+ years of ASIC/SoC RTL design experience
Preferred Qualifications: Expertise in microarchitecture development, RTL design, integration, and implementation
Cross-functional collaboration with architecture, verification, DFT, physical design, firmware, and systems teams
Knowledge of clock/reset architectures and low-power design
Experience with custom ISA processors, high-speed interconnects, and high-bandwidth I/O
Workload modeling and AI inference performance analysis
Translation Company Name: US6F Kinara Inc. USA