Principal ASIC Verification Engineer - DDR/LPDDR at Synopsys

Synopsys is hiring a DesignWare IP Verification Lead in Bangalore to lead verification engineers through full IP verification cycles, build and evolve scalable SystemVerilog/UVM environments, define test plans, debug complex checkers and assertions, drive functional and code coverage to closure, and manage regression infrastructure. The role requires a bachelor's or master's degree in electrical or electronics and communication engineering, at least 8 years of hands-on verification experience, and proven experience leading verification teams through IP project delivery.