Principal Design Engineer – High-Speed Interconnect at ARM

Arm is hiring a High-Speed Interconnect RTL Architect to own the microarchitecture, RTL development, and integration of PCIe, CXL, and UALink subsystems across multiple silicon products. The role translates system and protocol requirements into microarchitecture specifications, interfaces, register definitions, and synthesizable RTL; leads development through verification, synthesis preparation, and delivery; and collaborates with architecture, verification, performance, firmware, physical design, and implementation teams. The position requires 8+ years of relevant semiconductor experience, deep expertise in SystemVerilog and high-speed interconnects, and a bachelor’s or master’s degree in a related field. The role offers a hybrid arrangement requiring at least two office days per week and a salary range of $249,900-$338,100 per year.