Principal Design Engineer – High-Speed Interconnect at ARM

The role owns the microarchitecture, RTL development, and integration of high-speed interconnect subsystems across multiple silicon products, covering PCIe, CXL, and UALink. It translates system and protocol requirements into microarchitecture specifications, interfaces, register definitions, and synthesizable RTL; leads development through verification, synthesis preparation, and delivery; and collaborates with architecture, verification, performance, firmware, physical design, and implementation teams. The position requires 8+ years of relevant semiconductor experience, deep expertise in SystemVerilog and high-speed interconnects, and a bachelor’s or master’s degree or equivalent experience. The role supports a hybrid arrangement requiring at least two days per week in the office.