Description
Astera Labs is seeking a Design Verification Professional to perform functional verification of complex server, storage, and networking SoC or silicon designs. The role involves developing block-level and system-level verification plans, writing and executing UVM test sequences, collecting and closing coverage, debugging RTL failures, and creating VIP abstraction layers. Candidates must have at least 12 years of experience supporting or developing complex SoC/silicon products and strong expertise in PCIe and CXL protocols.
